The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are scaled down through various technology nodes, strained source/drain features (e.g., stressor regions) using epitaxial (epi) semiconductor materials and/or layers of compressive/tensile dielectric materials formed over the MOSFETs have been implemented to enhance carrier mobility and to improve device performance. Subsequently, in order to form a contact plug connecting an interconnection layer and the gate, drain, or source terminal of a MOSFET, different materials need to be at least partially removed in order to form an opening for forming the contact plug.